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S500
S500
RISC-V 64-bit Architecture IPs
S500:
ESWIN Computing S500 64-bit general-purpose processor is a high energy-efficient 64-bit RISC-V application-level CPU IP product that meets the RVA23-Profile.
It is 9-stage pipeline, dual-issue, in-order architecture. It supports multicores. A core cluster can have up to 4 cores inside.
It supports RVA23-Profile to meet the requirements of Android platform and contains Hypervisor-mode to realize virtualization.
It also supports the trusted execution environment to meet the system security requirements.
Optional E-Trace/Ntrace for advanced debugging function is supported.
It is high energy efficiency application cores and can be used in broad applications, such as AIoT edge computing, network devices, baseband communication and etc.
It is 9-stage pipeline, dual-issue, in-order architecture. It supports multicores. A core cluster can have up to 4 cores inside.
It supports RVA23-Profile to meet the requirements of Android platform and contains Hypervisor-mode to realize virtualization.
It also supports the trusted execution environment to meet the system security requirements.
Optional E-Trace/Ntrace for advanced debugging function is supported.
It is high energy efficiency application cores and can be used in broad applications, such as AIoT edge computing, network devices, baseband communication and etc.
Features
| Features | Description | ||||
| ISA | RVA23+Vector Crypto | ||||
| Multi-core | Single core, dual core, 4 core options | ||||
| Modes | Machine-mode, Hypervisor-mode, Supervisor-mode, User-mode | ||||
| Security | Supports ESWIN TEE solution, with up to 64 PMP regions | ||||
| Crypto | Support optional scalar, vector hardware encryption and decryption module | ||||
| Pipeline | 9-stage superscalar in-order pipeline, 2-way decode | ||||
| Branch Predictor | L0_BTB， BTB， IJTB，BHT， RAS， Loop Buffer | ||||
| L1 I$ | Size is configurable from 8KB to 64KB | ||||
| L1 D$ | Size is configurable from 8KB to 64KB | ||||
| Cluster LLC | Size is configurable from 256KB to 4MB | ||||
| MMU | SV39，ITLB，DTLB | ||||
| Interrupt | CLINT，PLIC | ||||
| Debug | Debug module: supports JTAG Debug module: supports JTAG Trace module: supports RISC-V standard E-Trace/ N-Trace |
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| Bus Interface | 1. Memory Port: 128–bit AXI master interface 2. Peripheral Port: 128-bit AXI master interface 3. Front port : 128-bit AXI slave interface |
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| Vector | Supports RVV1.0 | ||||
| CoreMark（CoreMarks/MHz） | 6.27 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 2.90 | ||||
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